Phase-locked loops (PLLs) are frequently used to synchronize a local clock of a digital device which receives data over a communication channel to the frequency and phase of the received digital data. One type of PLL utilizes a two-state quantized phase detector. In such a PLL, a serial logic representation of the leading and lagging phase errors provides a simple and low cost interface between the two-state quantized phase detector and a digitally controlled oscillator. The two logic states of the serial interface cause the output phase of the digitally controlled oscillator to advance or retard in response to the sign of the phase error.
In many high-speed data communication systems, such as the Fiber Distribution Data Interface (FDDI), duty-cycle distortions and data-pattern dependent jitters can be severe. In such systems, proportionate phase detectors, rather than two-state quantized state detectors, are commonly employed. Proportionate phase detectors, however, may use long digital words, which are costly to process. Accordingly, there is a need to embed proportionate phase error information in serial logic signals so as to insure that duty-cycle distortions and data-pattern dependent jitters can be kept within reasonable limits, and to allow implementation of the PLL using digital logic circuitry.
A prior art technique that might be adapted to achieve this goal is the use of a proportionate phase detector followed by a charge pump and a comparator. However, designing charge pumps for operation at high frequencies such as 100 megahertz and above is difficult. Charge pumps designed for operation at such high frequencies commonly suffer from performance problems such as dead band problems. Further, the P-channel and N-channel transistors of the complementary current sources used in such charge pumps are difficult to match, resulting in degradation of the PLL's dynamic tracking performance and causing static alignment errors (SAEs).
U.S. Pat. No. 5,239,561 discloses a phase error processor which substantially overcomes some of these problems. That patent discloses a phase error processor (PEP) which interfaces a proportionate phase detector to a digital loop filter in a high frequency PLL. The PLL receives a high frequency stream of NRZI encoded data. The data is received at a variable density of data signal transitions. A phase detector in the PLL generates proportionate phase error information in the form of a phase error signal PD1 and a reference signal PD2. PD1 is a pulse signal with a pulse width, TW1, that corresponds to the phase error between the data signal transition and the local PLL clock. PD2 is a pulse signal with a fixed width, TW2, equal to half of the period of the local PLL clock.
The PEP disclosed in that patent defines a window of N local clock cycles, where N is an integer. The PEP separately integrates the proportionate phase error pulses from just one pair of adjacent positive and negative data transitions on each of PD1 and PD2 during each window, if the number of input data transitions which occur during that window exceeds an expected minimum. Otherwise, the PEP passes no phase error information. The selection of window width (i.e., the value of N) is selected relative to the coding scheme of the incoming data stream to assure that the window is wide enough such that there will be at least two pulses per window under normal conditions. The integrated information on each signal, PD1 and PD2, is converted by the phase error processor once during each window into a single bit UP/DOWN signal which is provided to a digitally controlled oscillator (DCO) through a digital loop filter. The DCO, which is generating the local clock signal, advances or retards the phase of the local PLL clock depending on the condition of the UP/DOWN signal.
In particular, the PEP disclosed in U.S. Pat. No. 5,239,561 includes first and second integrator circuits for integrating the PB1 and PB2 signals, respectively. The outputs of the two integrators are coupled to the separate inputs of a comparator. The output of the comparator is coupled to the input of a D flip flop, which latches the comparator output signal once for each window. The output of the D flip flop is the UP/DOWN signal. The control of the DCO by the UP/DOWN signal should cause the clock output of the DCO to approach the frequency of the incoming data stream.
However, mismatch between the components of the two integrators (e.g., resistors and capacitors) causes a static alignment error (or SAE) between the local clock output by the DCO and the frequency of the incoming data stream. Further, any offset between the inputs of the comparator causes additional static alignment error.
Accordingly, it is an object of the present invention to provide an improved phase error processor for a PLL.
It is another object of the present invention to provide a phase error processor employing a comparator input swapping technique.
It is a further object of the present invention to provide a phase-error processor for a PLL in which mismatch of integrator componentry does not result in a static alignment error.
It is yet one more object of the present invention to provide a phase error processor for a PLL in which input offset of the comparator does not cause a static alignment error.